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femtoclocks? crystal-to-3.3v, 2.5v lvpecl clock generator ICS843241I-04 idt ? / ics ? 150mhz, 3.3v, 2.5v lvpeclclock generator 1 ics843241agi-04 rev. a may 1, 2008 preliminary g eneral d escription the ICS843241I-04 is a serial ata (sata)/serial attached scsi (sas) clock generator and a member of the hiperclocks tm family of high performance devices from idt. for sata/sas applications, a 25mhz crystal is used to produce 150mhz. the ICS843241I-04 is packaged in a small 8-pin tssop, making it ideal for use in systems with limited board space. f eatures ? one differential lvpecl output ? crystal oscillator interface, 18pf parallel resonant crystal (20.833mhz - 28.3mhz) ? maximum output frequency: 150mhz ? vco range: 500mhz - 680mhz ? rms phase jitter @ 150mhz, using a 25mhz crystal (12khz - 20mhz): 1.2ps (typical) ? 3.3v or 2.5v operating supply ? -40c to 85c ambient operating temperature ? available in both standard (rohs 5) and lead-free (rohs 6) packages hiperclocks? ic s b lock d iagram osc phase detector vco 500mhz - 680mhz m = 24 (fixed) n divider 4 q nq xtal_in xtal_out p in a ssignment v cca xtal_out xtal_in v ee 1 2 3 4 v cc q nq nc 8 7 6 5 ICS843241I-04 8-lead tssop 4.4mm x 3.0mm x 0.925mm package body g package top view the preliminary information presented herein represents a product in pre-production. the noted characteristics are based on ini tial product characterization and/or qualification. integrated device technology, incorporated (idt) reserves the right to change any circuitry or specificat ions without notice.
idt ? / ics ? 150mhz, 3.3v, 2.5v lvpeclclock generator 2 ics843241agi-04 rev. a may 1, 2008 ICS843241I-04 femtoclocks? crystal-to- 3.3v, 2.5v lvpecl clock generator preliminary t able 1. p in d escriptions r e b m u ne m a ne p y tn o i t p i r c s e d 1v a c c r e w o p. n i p y l p p u s g o l a n a , 2 3 , t u o _ l a t x n i _ l a t x t u p n i , t u p n i e h t s i n i _ l a t x . e c a f r e t n i r o t a l l i c s o l a t s y r c . t u p t u o e h t s i t u o _ l a t x 4v e e r e w o p. n i p y l p p u s e v i t a g e n 5c nt u p n i. t c e n n o c o n 7 , 6q , q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . s t u p t u o k c o l c l a i t n e r e f f i d 8v c c r e w o p. n i p y l p p u s e r o c
idt ? / ics ? 150mhz, 3.3v, 2.5v lvpeclclock generator 3 ics843241agi-04 rev. a may 1, 2008 ICS843241I-04 femtoclocks? crystal-to- 3.3v, 2.5v lvpecl clock generator preliminary t able 2a. p ower s upply dc c haracteristics , v cc = 3.3v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v c c e g a t l o v y l p p u s e r o c 5 3 1 . 33 . 35 6 4 . 3v v a c c e g a t l o v y l p p u s g o l a n av c c 0 1 . 0 ?3 . 3v c c v i c c t n e r r u c y l p p u s r e w o p 0 6a m i a c c t n e r r u c y l p p u s g o l a n a 0 1a m a bsolute m aximum r atings supply voltage, v dd 4.6v inputs, v i -0.5v to v cc + 0.5v outputs, i o contin uous current 50ma surge current 100ma package thermal impedance, ja 129.5c/w (0 mps) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional op- eration of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. t able 2c. lvcmos/lvttl dc c haracteristics , v cc = 3.3v5% or 2.5v5%, t a = -40c to 85c t able 2b. p ower s upply dc c haracteristics , v cc = 2.5v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v c c e g a t l o v y l p p u s e r o c 5 7 3 . 25 . 25 2 6 . 2v v a c c e g a t l o v y l p p u s g o l a n av c c 0 1 . 0 ?5 . 2v c c v i c c t n e r r u c y l p p u s r e w o p 0 6a m i a c c t n e r r u c y l p p u s g o l a n a 0 1a m l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i e g a t l o v h g i h t u p n i v c c v 3 . 3 =2v c c 3 . 0 +v v c c v 5 . 2 =7 . 1v c c 3 . 0 +v v l i e g a t l o v w o l t u p n i v c c v 3 . 3 =3 . 0 -8 . 0v v c c v 5 . 2 =3 . 0 -7 . 0v
idt ? / ics ? 150mhz, 3.3v, 2.5v lvpeclclock generator 4 ics843241agi-04 rev. a may 1, 2008 ICS843241I-04 femtoclocks? crystal-to- 3.3v, 2.5v lvpecl clock generator preliminary t able 3. c rystal c haracteristics r e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u n o i t a l l i c s o f o e d o m l a t n e m a d n u f y c n e u q e r f 3 3 8 . 0 23 . 8 2z h m ) r s e ( e c n a t s i s e r s e i r e s t n e l a v i u q e 0 5 e c n a t i c a p a c t n u h s 7f p l e v e l e v i r d 1w m t able 4a. ac c haracteristics , v cc = 3.3v5%, t a = -40c to 85c t able 4b. ac c haracteristics , v cc = 2.5v5%, t a = -40c to 85c t able 2d. lvpecl dc c haracteristics , v cc = 3.3v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f t u o y c n e u q e r f t u p t u o 0 5 1z h m t ) ? ( t i j ; ) m o d n a r ( r e t t i j e s a h p s m r 1 e t o n : e g n a r n o i t a r g e t n i @ z h m 0 5 1 z h m 0 2 - z h k 2 1 2 . 1s p t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 0 4s p c d oe l c y c y t u d t u p t u o 0 5% . n o i t c e s s i h t g n i w o l l o f t o l p e s i o n e s a h p e h t o t r e f e r e s a e l p : 1 e t o n l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f t u o y c n e u q e r f t u p t u o 0 5 1z h m t ) ? ( t i j ; ) m o d n a r ( r e t t i j e s a h p s m r 1 e t o n : e g n a r n o i t a r g e t n i @ z h m 0 5 1 z h m 0 2 - z h k 2 1 2 4 . 1s p t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 0 4s p c d oe l c y c y t u d t u p t u o 0 5% . n o i t c e s s i h t g n i w o l l o f t o l p e s i o n e s a h p e h t o t r e f e r e s a e l p : 1 e t o n l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h o 1 e t o n ; e g a t l o v h g i h t u p t u ov c c 4 . 1 -v c c 9 . 0 -v v l o 1 e t o n ; e g a t l o v w o l t u p t u ov c c 0 . 2 -v c c 7 . 1 -v v g n i w s g n i w s e g a t l o v t u p t u o k a e p - o t - k a e p6 . 00 . 1v 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n v o t c c . v 2 - t able 2e. lvpecl dc c haracteristics , v cc = 2.5v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h o 1 e t o n ; e g a t l o v h g i h t u p t u ov c c 4 . 1 -v c c 9 . 0 -v v l o 1 e t o n ; e g a t l o v w o l t u p t u ov c c 0 . 2 -v c c 5 . 1 -v v g n i w s g n i w s e g a t l o v t u p t u o k a e p - o t - k a e p4 . 00 . 1v 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n v o t c c . v 2 -
idt ? / ics ? 150mhz, 3.3v, 2.5v lvpeclclock generator 5 ics843241agi-04 rev. a may 1, 2008 ICS843241I-04 femtoclocks? crystal-to- 3.3v, 2.5v lvpecl clock generator preliminary t ypical p hase n oise at 150mh z (3.3v) 150mhz rms phase jitter (random) 12khz to 20mhz = 1.2ps (typical) o ffset f requency (h z ) ? ? ? dbc hz n oise p ower sata/sas jitter filter raw phase noise data phase noise result by adding a sata/sas filter to raw data t ypical p hase n oise at 150mh z (2.5v) 150mhz rms phase jitter (random) 12khz to 20mhz = 1.42ps (typical) ? ? ? dbc hz n oise p ower sata/sas jitter filter raw phase noise data phase noise result by adding a sata/sas filter to raw data o ffset f requency (h z )
idt ? / ics ? 150mhz, 3.3v, 2.5v lvpeclclock generator 6 ics843241agi-04 rev. a may 1, 2008 ICS843241I-04 femtoclocks? crystal-to- 3.3v, 2.5v lvpecl clock generator preliminary p arameter m easurement i nformation rms p hase j itter 3.3v o utput l oad ac t est c ircuit 2.5v o utput l oad ac t est c ircuit o utput r ise /f all t ime o utput d uty c ycle /p ulse w idth /p eriod t pw t period t pw t period odc = x 100% q nq phase noise mas k offset frequency f 1 f 2 phase noise plot rms jitter = area under the masked phase noise plot noise power scope qx nqx lvpecl v ee 2v -1.3v 0.165v v cc 2v v cca scope qx nqx lvpecl v ee 2v -0.5v 0.125v v cc 2v v cca 20% 80% 80% 20% t r t f v sw i n g q nq
idt ? / ics ? 150mhz, 3.3v, 2.5v lvpeclclock generator 7 ics843241agi-04 rev. a may 1, 2008 ICS843241I-04 femtoclocks? crystal-to- 3.3v, 2.5v lvpecl clock generator preliminary a pplication i nformation f igure 1. p ower s upply f iltering 10 v cca 10 f .01 f 3.3v or 2.5v .01 f v cc f igure 2. c rystal i npu t i nterface c rystal i nput i nterface the ICS843241I-04 has been characterized with 18pf parallel resonant crystals. the capacitor values, c1 and c2, shown in figure 2 below were determined using a 25mhz, 18pf parallel resonant crystal and were chosen to minimize the ppm error. the optimum c1 and c2 values can be slightly adjusted for different board layouts. xtal_in xtal_out x1 18pf parallel crystal c1 33p c2 33p p ower s upply f iltering t echniques as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. to achieve optimum jitter perfor- mance, power supply isolation is required. the i cs843241i-04 provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v cc and v cca should be individually connected to the power supply plane through vias, and 0.01f bypass capacitors should be used for each pin. fig- ure 1 illustrates this for a generic v cc pin and also shows that v cca requires that an additional10 resistor along with a 10f bypass capacitor be connected to the v cca pin.
idt ? / ics ? 150mhz, 3.3v, 2.5v lvpeclclock generator 8 ics843241agi-04 rev. a may 1, 2008 ICS843241I-04 femtoclocks? crystal-to- 3.3v, 2.5v lvpecl clock generator preliminary t ermination for 3.3v lvpecl o utputs the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are rec- ommended only as guidelines. fout and nfout are low impedance follower outputs that gen- erate ecl/lvpecl compatible outputs. therefore, terminating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to drive 50 f igure 4b. lvpecl o utput t ermination f igure 4a. lvpecl o utput t ermination transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal dis- tortion. figures 4a and 4b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board design- ers simulate to guarantee compatibility across all printed circuit and clock component process variations. v cc - 2v 50 50 rtt z o = 50 z o = 50 fout fin rtt = z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v 125 125 84 84 z o = 50 z o = 50 fout fin lvcmos to xtal i nterface the xtal_in input can accept a single-ended lvcmos signal through an ac coupling capacitor. a general interface diagram is shown in figure 3. the xtal_out pin can be left floating. the input edge rate can be as slow as 10ns. for lvcmos inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. this configuration requires that the output f igure 3. g eneral d iagram for lvcmos d river to xtal i nput i nterface impedance of the driver (ro) plus the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 applications, r1 and r2 can be 100 . this can also be accomplished by removing r1 and making r2 50 . r2 zo = 50 vdd ro zo = ro + rs r1 vdd xta l _i n xta l _o u t .1uf rs
idt ? / ics ? 150mhz, 3.3v, 2.5v lvpeclclock generator 9 ics843241agi-04 rev. a may 1, 2008 ICS843241I-04 femtoclocks? crystal-to- 3.3v, 2.5v lvpecl clock generator preliminary t ermination for 2.5v lvpecl o utputs figure 5a and figure 5b show examples of termination for 2.5v lvpecl driver. these terminations are equivalent to terminating 50 to v cc - 2v. for v cc = 2.5v, the v cc - 2v is very close to ground level. the r3 in figure 5b can be eliminated and the termination is shown in figure 5c. f igure 5c. 2.5v lvpecl t ermination e xample f igure 5b. 2.5v lvpecl d river t ermination e xample f igure 5a. 2.5v lvpecl d river t ermination e xample r2 62.5 zo = 50 ohm r1 250 + - 2.5v 2,5v lvpecl driv er r4 62.5 r3 250 zo = 50 ohm 2.5v vcc=2.5v r1 50 r3 18 zo = 50 ohm zo = 50 ohm + - 2,5v lvpecl driv er vcc=2.5v 2.5v r2 50 2,5v lvpecl driv er vcc=2.5v r1 50 r2 50 2.5v zo = 50 ohm zo = 50 ohm + -
idt ? / ics ? 150mhz, 3.3v, 2.5v lvpeclclock generator 10 ics843241agi-04 rev. a may 1, 2008 ICS843241I-04 femtoclocks? crystal-to- 3.3v, 2.5v lvpecl clock generator preliminary p ower c onsiderations this section provides information on power dissipation and junction temperature for the ICS843241I-04. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ICS843241I-04 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v cc_max * i ee_max = 3.465v * 60ma = 207.9mw ? power (outputs) max = 30mw/loaded output pair total power _max (3.465v, with all outputs switching) = 207.9mw + 30mw = 237.9mw 2. junction temperature. junction temperature, tj, is the t emperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 129.5c/w per table 5 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.238w * 129.5c/w = 115.8c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer). t able 5. t hermal r esistance ja for 8- pin tssop, f orced c onvection 0 1 2.5 multi-layer pcb, jedec standard test boards 129.5c/w 125.5c/w 123.5c/w ja by velocity (meters per second)
idt ? / ics ? 150mhz, 3.3v, 2.5v lvpeclclock generator 11 ics843241agi-04 rev. a may 1, 2008 ICS843241I-04 femtoclocks? crystal-to- 3.3v, 2.5v lvpecl clock generator preliminary 3. calculations and equations. the purpose of this section is to derive the power dissipated into the load. lvpecl output driver circuit and termination are shown in figure 6. t o calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of v cc ? 2v. ? for logic high, v out = v oh_max = v cc_max ? 0.9v (v cc_max ? v oh_max ) = 0.9v ? for logic low, v out = v ol_max = v cc_max ? 1.7v (v cc_max ? v ol_max ) = 1.7v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cc_max ? 2v))/r l ] * (v cc_max ? v oh_max ) = [(2v - (v cc_max ? v oh_max )) /r l ] * (v cc_max ? v oh_max ) = [(2v ? 0.9v)/50 ] * 0.9v = 19.8mw pd_l = [(v ol_max ? (v cc_max ? 2v))/r l ] * (v cc_max ? v ol_max ) = [(2v ? (v cc_max ? v ol_max )) /r l ] * (v cc_max ? v ol_max ) = [(2v ? 1.7v)/50 ] * 1.7v = 10.2mw total power dissipation per output pair = pd_h + pd_l = 30mw f igure 6. lvpecl d river c ircuit and t ermination q1 v out v cco rl 50 v cco - 2v
idt ? / ics ? 150mhz, 3.3v, 2.5v lvpeclclock generator 12 ics843241agi-04 rev. a may 1, 2008 ICS843241I-04 femtoclocks? crystal-to- 3.3v, 2.5v lvpecl clock generator preliminary r eliability i nformation t ransistor c ount the transistor count for ICS843241I-04 is: 1732 t able 6. ja vs . a ir f low t able for 8 l ead tssop ja by velocity (meters per second) 0 1 2.5 multi-layer pcb, jedec standard test boards 129.5c/w 125.5c/w 123.5c/w p ackage o utline - g s uffix for 8 l ead tssop t able 7. p ackage d imensions reference document: jedec publication 95, mo-153 l o b m y s s r e t e m i l l i m m u m i n i mm u m i x a m n8 a- -0 2 . 1 1 a5 0 . 05 1 . 0 2 a0 8 . 05 0 . 1 b9 1 . 00 3 . 0 c9 0 . 00 2 . 0 d0 9 . 20 1 . 3 ec i s a b 0 4 . 6 1 e0 3 . 40 5 . 4 ec i s a b 5 6 . 0 l5 4 . 05 7 . 0 0 8 a a a- -0 1 . 0 p ackage o utline and d imensions
idt ? / ics ? 150mhz, 3.3v, 2.5v lvpeclclock generator 13 ics843241agi-04 rev. a may 1, 2008 ICS843241I-04 femtoclocks? crystal-to- 3.3v, 2.5v lvpecl clock generator preliminary while the information presented herein has been checked for both accuracy and reliability, integrated device technology, incorp orated (idt) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications such as those requiring high reliability or other extraordinary environmental r equirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments. t able 8. o rdering i nformation r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t 4 0 - i g a 1 4 2 3 4 8 s c i4 0 i a 1p o s s t d a e l 8e b u tc 5 8 o t c 0 4 - t 4 0 - i g a 1 4 2 3 4 8 s c i4 0 i a 1p o s s t d a e l 8l e e r & e p a t 0 0 5 2c 5 8 o t c 0 4 - f l 4 0 - i g a 1 4 2 3 4 8 s c id b tp o s s t " e e r f - d a e l " d a e l 8e b u tc 5 8 o t c 0 4 - t f l 4 0 - i g a 1 4 2 3 4 8 s c id b tp o s s t " e e r f - d a e l " d a e l 8l e e r & e p a t 0 0 5 2c 5 8 o t c 0 4 - . t n a i l p m o c s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s " f l " n a h t i w d e r e d r o e r a t a h t s t r a p : e t o n
ICS843241I-04 femtoclocks? crystal-to- 3.3v, 2.5v lvpecl clock generator preliminary innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt for tech support netcom@idt.com +480-763-2056 corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800-345-7015 (inside usa) +408-284-8200 (outside usa) ? 2008 integrated device technology, inc. all rights reserved. product spe cifications subject to change without notice. idt, th e idt logo, ics and hiperclocks are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa

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